The present invention relates to microprocessor bus controllers, and in particular, bus controllers which incorporate state machine technology for providing various bus operation types and bus timing variations.
In the past, bus controllers were integrated into and functioned as part of the microprocessor architecture. As microprocessor technology advanced, bus controller technology became separate and distinct. As the number of peripheral devices available for use with various microprocessors became available, it became obvious that peripheral devices usable with one integrated microprocessor bus controller architecture could not generally be used with the bus controller of another microprocessor.
Separate microprocessor and bus controller architectures provide system design flexibility, as well as facilitating interface of many peripheral devices among many different microprocessors. In the present state of the art, microprocessors are expected to interface with memory management units, CRT controllers, floppy disk controllers, hard disk controllers, arithmetic co-processors and the like. In addition, it is well known that the next generation of 32-bit microprocessors must be able to interface with already existing peripheral devices without the immediate need for specially designed bus controllers.
However, even though microprocessor and bus controller architectures are separated, bus controllers designed to interface with a specific type or range of types of microprocessors and peripheral devices are still limited to certain system configurations and further limit design flexibilities for the next generation of microprocessors. See, for example, the well-known personal computer models known as the "PC XT" and "PC AT", manufactured and sold by the IBM Corporation.
In the past, I/O bus structures in small micro-computer based systems comprised little more than buffered extensions of the microprocessor I/O pins. While microprocessor speeds, architecture and I/O protocols evolve at a rapid rate, system level I/O channel configurations remain essentially unchanged in structure and timing for 5 to 10 years. The present invention provides a simple means to accurately synthesize a given set of I/O bus protocols and timings which can be achieved with a wide spectrum of microprocessor types and speeds.
The state machine bus controller of the present invention enables designers to change the functionality of a controller bus quickly and inexpensively. While typically the control function is completely synchronous, whereby the microprocessor and bus may work in lock step, the design of the bus controller of the present invention is able to interface with a bus which is synchronous or asynchronous in nature, thus providing the flexibility to interface with more than one type of microprocessor at one interface, and more than one type of peripheral or memory devices at the other interface.
The state machine bus controller can maintain a synchronous protocol or handshake with the microprocessor (or CPU), while providing signals with sufficient function and timing parameters to satisfy the requirements of an asynchronous bus and various devices which can reside on the bus. While the use of a state machine within a bus controller provides the ability to change the function and timing of various signals quickly and easily, it also can provide the means to change the bus cycle functionality and timing (in a dynamic sense) owing to bus conditions or in response to specific access requests. Much of the way in which the bus controller of the present invention accomplishes the interface between the bus and the CPU is through the control of data path steering buffers commonly used in small micro-computer based systems.
State machine technology, generally, is well-known. See, for example:
Mealy, G. H.: A Method for Synthesizing Sequential Circuits, Bell System Tech. J., vol. 34, pp. 1045-1079, September 1955. PA1 Moore, E. F., "Gedanken-experiments on Sequential Machines," pp. 129-153, Automata Studies, Princeton University Press, Princeton, N.J., 1956.
In the present invention, synchronous signals are generated by clocked flip flops and all of the feedback loops in the state machine are functions clocked at the same rate. The state machine uses the information which is available at the input of the bus controller as well as the current machine state, i.e. a derivative of what happened last in the state machine, to determine what the next machine state will be and what signals or functions to provide. Input information is received by the controller of the present invention from the microprocessor and from the device which the microprocessor is trying to access via the bus itself.
Information from the microprocessor starts an access cycle. Information returning from the accessed device via the bus can modify how the cycle proceeds and the timing of the cycle. The state machine also uses information returning from the accessed device, as well as the current state of the machine, to control the microprocessor. Finally, when the cycle is complete, the controller produces a signal, so notifying the microprocessor that it is ready for the next access request.
The state machine bus controller of the present invention can emulate the function of prior art bus controllers and anticipate the more and different functions of bus controllers of future systems. Since bus controllers generally are sequential in operation and provide finite numbers of bus operation types and timing variations thereof, bus control functions may be provided and controlled by a state machine. Owing to the flexibility of design based on state machine concepts, the bus controller of the present invention can change the direction of a path, jump to another path while in the middle of a current path as well as provide other system operational flexibilities described elsewhere in this application. Some bus signals which are not valid in the beginning of a cycle can be sampled later in the cycle when they become valid, thus changing the timing or function of that particular bus cycle. The state machine bus controller of the present invention generates both bus functions and the timing thereof.